The scaling of CMOS technology has been a driving force for area and power reduction of Very Large Scale Integration (VLSI) integrated circuits. Each generation of CMOS technology has produced a well predicted cost and energy reduction in proportional to the scaling of the size of minimum transistors. For area reduction, besides the technology scaling, the rapid development of highly efficient synthesis tools utilize sophisticated logic optimization method to eventually produce the minimum technology mapping of target functionality. On the other hand, the energy of conventional CMOS circuits are proportional to CV2 where C is the capacitance of the circuits defined by the logic functionality and further optimized by design automation tools. Hence, the reduction of energy consumption of the logic circuits has been mainly relying on the reduction of supply voltages. For example, tremendous efforts have been put on developing near-threshold computing technique to reduce the energy consumption of the chip. Meanwhile, many emerging low power techniques have been developed. For example, many variety of Razor technique have been proposed to detect timing error and recover the pipeline operation allowing supply voltage to scale beyond its nominal rating.
Recently, approximating computing has drawn significant attention by showing significant energy efficiency improvement if small errors can be tolerated. Although not all applications are error tolerant, large amount of emerging applications such as image processing, facial recognition, and the more recent neuromorphic computing are all in favor of trading off small amount of accuracy for power consumption which has been the bottleneck of modern battery operated devices. Similarly, previously proposed stochastic computing exploits the statistical significance of the computation and introduces error correction scheme to correct error from the most-significant bits due to voltage overscaling. Essentially, a new design optimization space is explored where functionality is slightly traded off in exchange of a large return of the energy consumption. Despite of the different methodologies used in various low power design techniques, the energy reduction has all relied on voltage scaling leaving the C relatively fixed from the logic synthesis.
The analog signal processing which has well been explored decades ago, offers several attractive features: (1) Because multiple bits information can be encoded within single signal at multiple voltage levels, it offers more energy efficient way for signal generation and processing compared with bit-wise digital signals; (2) Analog signal processing is more error resilient because the error probability drops exponentially with the position of significant bit. As a result, there is an increase of interest on utilizing analog signal processing for conventional digital signal processing applications. However, significant drawbacks also exist for analog signal processing. First of all, the static current consumption from an analog circuit can offset its energy benefits especially for low power design where the switching frequency is low. Secondly, the requirement of headroom for analog circuits to remain in saturation prevent the design from using low supply voltages causing diminishing benefits from technology scaling. As a result, analog signal processing has not been used prevalently for providing energy or area benefits.
To reduce the cost of integrated circuits, the chip area needs to be reduced but may not be possible due to the required functionality. Similarly, the energy consumption is limited by the required functionality. Conventional integrated circuits for digital signal processing have reached a bottleneck of energy and area consumption and are hard to be improved. Known conventional design methodology cannot further reduce area and energy of the design.
Time domain signal processing has been previously introduced, but (1) previous works utilized a conventional delay unit based on standard cells which are not energy efficient, fundamentally limiting the benefits of the previous work. As a result, no energy benefits was reported despite of the promise of the technique. (2) No systematic design methodology and modeling technique has been provided for designing a general purpose TDSP circuits. (3) Only special design of a Low-density Parity-Check (LDCP) was presented in previous works leaving the design strategy unknown for more generally used building blocks of signal processing, such as multiplier.